Chip package structure and manufacturing method thereof
US10950588B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2018 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Sep 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6755
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.