Single poly non-volatile memory device, method of manufacturing the same and single poly non-volatile memory device array
US10950614B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 17, 2020 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Aug 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.