Patent · US Active

Flip flop standard cell

US10951201B2 · kind B2 · utility

3Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 31, 2019
Grant dateMar 16, 2021
Priority date
Expiry dateMay 31, 2039

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C2207/007
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.