Synchronization of clock signals generated using output dividers
US10951216B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Oct 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.