Yield-oriented design-for-test in power-switchable cores
US10955472B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.