Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP)
US10956327B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Jun 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to systems and methods structured to mitigate cache conflicts through hardware assisted redirection of pages. In one example, a processor includes a translation cache to store a physical to slice mapping in response to a cache conflict mitigation request corresponding to a page; and a cache controller to determine whether the translation cache comprises the physical to slice mapping; determine whether one of a plurality of slices in a translation table comprises the physical to slice mapping if the translation cache does not comprise the physical to slice mapping, the translation table communicably coupled to a non-volatile memory; and if the translation table does not comprise the physical to slice mapping, redirect the cache conflict mitigation request to the non-volatile memory; and allocate a new physical to slice mapping for the page to one of the plurality of slices in the translation table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.