Charge pump supply optimization and noise reduction method for logic systems
US10957364B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Sep 26, 2018 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Apr 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.