Method of test and repair of memory cells during power-up sequence of memory device
US10957414B1 · kind B1 · utility
1Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a memory device for testing and repairing memory cells during a power-up sequence are provided. The memory device includes a built-in self test (BIST) unit for testing a memory cell array during the power-up sequence. The BIST unit performs a test on the memory cell array in response to a power stabilization signal, or performs a test on the memory cell array in response to an impedance control (ZQ) calibration command. The BIST unit terminates a test being performed in response to a write leveling command, or terminates a test being performed in response to an active command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.