Fin-based anti-fuse device for integrated circuit (IC) products, methods of making such an anti-fuse device and IC products comprising such an anti-fuse device
US10957701B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Nov 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One IC product disclosed herein includes, among other things, a semiconductor substrate, a first anti-fuse device formed on the semiconductor substrate, the first anti-fuse device comprising at least one first fin formed with a first fin pitch, a first source region and a first drain region, wherein the first anti-fuse device is adapted to breakdown when a first programing voltage is applied to the first anti-fuse device, and a second anti-fuse device formed on the semiconductor substrate, the second anti-fuse device comprising at least one second fin formed with a second fin pitch, a second source region and a second drain region, wherein the second anti-fuse device is adapted to breakdown when a second programing voltage is applied to the second anti-fuse device, wherein the first fin pitch is greater than the second fin pitch and wherein the first programming voltage is greater than the second programing voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.