Patent · US Active

3D NAND flash memory device and integration method thereof

US10963191B1 · kind B1 · utility

1Cited by
1References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 17, 2020
Grant dateMar 30, 2021
Priority date
Expiry dateJun 17, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/27
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

An integration method for a 3D NAND flash memory device includes disposing a plurality of 3D triple-level cell (TLC) NAND flash memories on a CMOS die; disposing at least a NOR Flash memory on the CMOS die of the 3D NAND flash memory device; and connecting the at least a NOR Flash memory to an Open NAND Flash Interface (ONFI) of the 3D NAND flash memory device; wherein the at least a NOR Flash memory is disposed on an unused area of the CMOS die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.