Systems and methods for performing 16-bit floating-point matrix dot product instructions
US10963246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2018 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jan 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.