Raanan Sade
100Patents
12h-index
112Co-inventors
85Inventor score
Filing activity: Dec 4, 2008 → Jan 22, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10719323B2 | Systems and methods for performing matrix compress and decompress instructions | Physics | 46 | Active |
| US10896043B2 | Systems for performing instructions for fast element unpacking into 2-dimensional registers | Physics | 28 | Active |
| US10990396B2 | Systems for performing instructions to quickly convert and use tiles as 1D vectors | Physics | 23 | Active |
| US10970076B2 | Systems and methods for performing instructions specifying ternary tile logic operations | Physics | 22 | Active |
| US10866786B2 | Systems and methods for performing instructions to transpose rectangular tiles | Physics | 20 | Active |
| US10963256B2 | Systems and methods for performing instructions to transform matrices into row-interleaved format | Physics | 20 | Active |
| US11093247B2 | Systems and methods to load a tile register pair | Physics | 19 | Active |
| US10963246B2 | Systems and methods for performing 16-bit floating-point matrix dot product instructions | Physics | 19 | Active |
| US11023235B2 | Systems and methods to zero a tile register pair | Physics | 19 | Active |
| US11080048B2 | Systems, methods, and apparatus for tile configuration | Physics | 13 | Active |
| US11023382B2 | Systems, methods, and apparatuses utilizing CPU storage with a memory reference | Physics | 13 | Active |
| US11579883B2 | Systems and methods for performing horizontal tile operations | Physics | 12 | Active |
| US11669326B2 | Systems, methods, and apparatuses for dot product operations | Physics | 11 | Active |
| US10162694B2 | Hardware apparatuses and methods for memory corruption detection | Physics | 11 | Active |
| US8352683B2 | Method and system to reduce the power consumption of a memory device | Emerging Cross-Sectional Technologies | 10 | Active |
| US9858140B2 | Memory corruption detection | Physics | 10 | Active |
| US11816036B2 | Method and system for performing data movement operations with read snapshot and in place write update | Physics | 9 | Active |
| US11809869B2 | Systems and methods to store a tile register pair to memory | Physics | 9 | Active |
| US11816483B2 | Systems, methods, and apparatuses for matrix operations | Physics | 8 | Active |
| US8806101B2 | Metaphysical address space for holding lossy metadata in hardware | Physics | 8 | Active |
| US8799582B2 | Extending cache coherency protocols to support locally buffered data | Physics | 7 | Active |
| US11249761B2 | Systems and methods for performing matrix compress and decompress instructions | Physics | 6 | Active |
| US10838734B2 | Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data | Physics | 6 | Active |
| US8627017B2 | Read and write monitoring attributes in transactional memory (TM) systems | Physics | 6 | Active |
| US11507376B2 | Systems for performing instructions for fast element unpacking into 2-dimensional registers | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.