Packed data element predication processors, methods, systems, and instructions
US10963257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Sep 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.