Prefetching in a lower level exclusive cache hierarchy
US10963388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Sep 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one general aspect, an apparatus may include a multi-tiered cache system that includes at least one upper cache tier relatively closer, hierarchically, to a processor and at least one lower cache tier relatively closer, hierarchically, to a system memory. The apparatus may include a memory interconnect circuit hierarchically between the multi-tiered cache system and the system memory. The apparatus may include a prefetcher circuit coupled with a lower cache tier of the multi-tiered cache system, and configured to issue a speculative prefetch request to the memory interconnect circuit for data to be placed into the lower cache tier. The memory interconnect circuit may be configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the multi-tiered cache system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.