Analyzing clock jitter using delay calculation engine
US10963610B1 · kind B1 · utility
1Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | May 22, 2020 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | May 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present embodiments are generally directed to analyzing clock jitter. Jitter affects the clock delay of the circuit and the time the clock is available at sync points, so it is important to calculate its impact correctly to take appropriate margin during timing analysis. Jitter could be due to various reasons—one of them is due to IR Impact on the Clock Tree. IR drop variations between the two consecutive cycles can effectively reduce the available clock period for data to be correctly captured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.