System, method for training and applying defect classifiers in wafers having deeply stacked layers
US10964013B2 · kind B2 · utility
1Cited by
7References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 5, 2018 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jun 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and non-transitory computer readable medium are provided for training and applying defect classifiers in wafers having deeply stacked layers. In use, a plurality of images generated by an inspection system for a location of a defect detected on a wafer by the inspection system are acquired. The location on the wafer is comprised of a plurality of stacked layers, and each image of the plurality of images is generated by the inspection system at the location using a different focus setting. Further, a classification of the defect is determined, utilizing the plurality of images.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.