Compute-in-memory bit cell
US10964356B2 · kind B2 · utility
3Cited by
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30Claims
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Key dates
| Filing date | Dec 6, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Dec 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.