Semiconductor package and method of manufacturing same
US10964656B2 · kind B2 · utility
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16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jun 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.