Three-dimensional semiconductor memory device
US10964714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jan 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.