Semiconductor device having fin-end stress-inducing features
US10964800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2016 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Dec 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.