Methodology and structure for field plate design
US10964810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Sep 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.