Sigma-delta modulation quantization error reduction technique for fractional-N phase-locked loop (PLL)
US10965297B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2020 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jun 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/193
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses are provided for fractional-N frequency synthesis using a phase-locked loop (PLL). A phase detector (PD) of the PLL determines a phase difference between a clock and a feedback clock (CLKFB). A low-pass loop filter of the PLL detects a control voltage based on the phase difference. A voltage-controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage. A sigma-delta modulator (SDM) of the PLL generates a division sequence ratio and a selection control signal based on a frequency command word. A multi-modulus divider (MMDIV) generates a first CLKFB and a second CLKFB based on the division sequence ratio and differential inputs of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.