High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimization
US10965300B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2020 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jun 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.