Low-power, low-latency time-to-digital-converter-based serial link
US10965442B2 · kind B2 · utility
1Cited by
18References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2018 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Oct 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.