Methods for optimizing circuit performance via configurable clock skews
US10969820B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | May 17, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | May 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.