Patent · US Active

Broadside random access memory for low cycle memory access and additional functions

US10970074B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Thomas Anton Leyrer · Geisenhausen, DE
William Cronin Wallace · Richardson, US
David Alston Lide · Rockville, US
Pratheesh Gangadhar Thalakkal K{dot over (o)}ttilaveedu · Bengaluru, IN

Key dates

Filing date	May 29, 2019
Grant date	Apr 6, 2021
Priority date	—
Expiry date	May 29, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/306
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.