Thomas Anton Leyrer
26Patents
3h-index
15Co-inventors
60Inventor score
Filing activity: Mar 27, 1995 → Jul 29, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5729713A | Data processing with first level cache bypassing after a data transfer becomes excessively long | Emerging Cross-Sectional Technologies | 14 | Expired |
| US5664230A | Data processing with adaptable external burst memory access | Physics | 10 | Expired |
| US5860027A | System for receiving burst width greater than cache width by storing first portion of burst to cache and storing second portion of burst to storage circuit | Physics | 5 | Expired |
| US6948013B2 | Apparatus and method for configuring data cells | Electricity | 3 | Expired |
| US11281493B2 | Real-time context specific task manager for multi-core communication and control system | Physics | 1 | Active |
| US8130791B2 | Receiver and method for processing a stream of data packets when an error occurred on the physical layer | Electricity | 1 | Active |
| US11048552B2 | High-speed broadside communications and control system | Physics | 1 | Active |
| US11336757B2 | Sample based data transmission over low-level communication channel | Physics | 0 | Active |
| US11075707B2 | Open real-time ethernet protocol | Electricity | 0 | Active |
| US11579877B2 | Broadside random access memory for low cycle memory access and additional functions | Physics | 0 | Active |
| US11875183B2 | Real-time arbitration of shared resources in a multi-master communication and control system | Physics | 0 | Active |
| US6707902B2 | Method of resynchronizing data transfer between two modems connected by a dedicated line | Electricity | 0 | Expired |
| US11243809B2 | Level two first-in-first-out transmission | Physics | 0 | Active |
| US10871992B2 | Level two first-in-first-out transmission | Physics | 0 | Active |
| US11405121B2 | Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network | Electricity | 0 | Active |
| US12113612B2 | Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network | Electricity | 0 | Active |
| US10970074B2 | Broadside random access memory for low cycle memory access and additional functions | Physics | 0 | Active |
| US12086632B2 | Real-time context specific task manager for multi-core communication and control system | Physics | 0 | Active |
| US10484119B2 | Open real-time ethernet protocol | Electricity | 0 | Active |
| US11290099B2 | Managing pulse-width modulation trip signals from multiple sources | Electricity | 0 | Active |
| US10396922B2 | Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network | Electricity | 0 | Active |
| US12040885B2 | Open real-time ethernet protocol | Electricity | 0 | Active |
| US10812060B2 | Managing pulse-width modulation trip signals from multiple sources | Electricity | 0 | Active |
| US11704154B2 | High-speed broadside communications and control system | Physics | 0 | Active |
| US11966777B2 | Level two first-in-first-out transmission | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.