Systems and methods for performing instructions specifying ternary tile logic operations
US10970076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2018 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Sep 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to systems and methods for performing instructions specifying ternary tile operations. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction specifying a ternary tile operation, and locations of destination and first, second, and third source matrices, each of the matrices having M rows by N columns; and execution circuitry to respond to the decoded instruction by, for each equal-sized group of K elements of the specified first, second, and third source matrices, generate K results by performing the ternary tile operation in parallel on K corresponding elements of the specified first, second, and third source matrices, and store each of the K results to a corresponding element of the specified destination matrix, wherein corresponding elements of the specified source and destination matrices occupy a same relative position within their associated matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.