Cache snooping mode extending coherence protection for certain requests
US10970215B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Dec 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a flush/clean memory access operation of one of a plurality of processor cores that specifies a target address, services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores such that no other coherence participant is permitted to assume coherence ownership of the memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.