Guy L. Guthrie
472Patents
30h-index
115Co-inventors
93Inventor score
Filing activity: Sep 5, 1991 → Dec 21, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5784576A | Method and apparatus for adding and removing components of a data processing system without powering down | Physics | 164 | Expired |
| US6748518B1 | Multi-level multiprocessor speculation mechanism | Physics | 98 | Expired |
| US5898888A | Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system | Physics | 86 | Expired |
| US6405289B1 | Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response | Physics | 82 | Expired |
| US5613153A | Coherency and synchronization mechanisms for I/O channel controllers in a data processing system | Physics | 79 | Expired |
| US6691220B1 | Multiprocessor speculation mechanism via a barrier speculation flag | Physics | 74 | Expired |
| US6591321B1 | Multiprocessor system bus protocol with group addresses, responses, and priorities | Physics | 67 | Expired |
| US6625660B1 | Multiprocessor speculation mechanism for efficiently managing multiple barrier operations | Physics | 64 | Expired |
| US6880073B2 | Speculative execution of instructions and processes before completion of preceding barrier operations | Physics | 63 | Expired |
| US6393528B1 | Optimized cache allocation algorithm for multiple speculative requests | Physics | 60 | Expired |
| US6848003B1 | Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response | Physics | 55 | Expired |
| US7073043B2 | Multiprocessor system supporting multiple outstanding TLBI operations per partition | Physics | 54 | Expired |
| US5673399A | System and method for enhancement of system bus to mezzanine bus transactions | Physics | 49 | Expired |
| US6963967B1 | System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture | Physics | 43 | Expired |
| US6704843B1 | Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange | Physics | 41 | Expired |
| US6609192B1 | System and method for asynchronously overlapping storage barrier operations with old and new storage operations | Physics | 41 | Expired |
| US7469318B2 | System bus structure for large L2 cache array topology with different latency domains | Emerging Cross-Sectional Technologies | 40 | Active |
| US6470427B1 | Programmable agent and method for managing prefetch queues | Physics | 40 | Expired |
| US6345342B1 | Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line | Physics | 38 | Expired |
| US6748501B2 | Microprocessor reservation mechanism for a hashed address system | Physics | 35 | Expired |
| US6601144B1 | Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis | Physics | 34 | Expired |
| US7272773B2 | Cache directory array recovery mechanism to support special ECC stuck bit matrix | Physics | 32 | Expired |
| US7047320B2 | Data processing system providing hardware acceleration of input/output (I/O) communication | Physics | 31 | Expired |
| US6785774B2 | High performance symmetric multiprocessing systems via super-coherent data mechanisms | Physics | 31 | Expired |
| US6606702B1 | Multiprocessor speculation mechanism with imprecise recycling of storage operations | Physics | 31 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.