Dynamic bit-scan techniques for memory device programming
US10971222B2 · kind B2 · utility
0Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Dec 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.