Measurement of MTJ in a compact memory array
US10971245B1 · kind B1 · utility
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16Claims
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Key dates
| Filing date | Sep 20, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Sep 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for testing a magnetic memory cell in a bit cell array to determine whether the electrical resistance values of the memory cell are within acceptable parameters. The system and method allows for the determination of the electrical resistance of the memory cell without parasitic resistance associated with that memory cell in order to accurately determine the electrical resistance of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.