Memory devices and methods of manufacturing thereof
US10971505B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2020 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.