Yih Wang
167Patents
3h-index
72Co-inventors
63Inventor score
Filing activity: Jan 3, 2017 → Jul 3, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11404091B2 | Memory array word line routing | Electricity | 10 | Active |
| US10971505B1 | Memory devices and methods of manufacturing thereof | Electricity | 4 | Active |
| US11776595B2 | Memory device with source line control | Physics | 3 | Active |
| US11563015B2 | Memory devices and methods of manufacturing thereof | Electricity | 3 | Active |
| US11238904B1 | Using embedded switches for reducing capacitive loading on a memory system | Physics | 3 | Active |
| US11532752B2 | Non-volatile memory device with reduced area | Electricity | 3 | Active |
| US11735280B2 | Memory device and operating method of the same | Electricity | 3 | Active |
| US11601117B1 | Sense amplifier for coupling effect reduction | Electricity | 3 | Active |
| US11521663B2 | Memory circuit and method of operating same | Physics | 3 | Active |
| US11094387B2 | Multi-fuse memory cell circuit and method | Electricity | 3 | Active |
| US11018260B2 | Non-volatile memory device with reduced area | Electricity | 3 | Active |
| US11532746B2 | Multi-bit memory storage device and method of operating same | Electricity | 3 | Active |
| US11238906B2 | Series of parallel sensing operations for multi-level cells | Physics | 2 | Active |
| US11088151B2 | 4Cpp SRAM cell and array | Physics | 2 | Active |
| US11756591B2 | Switches to reduce routing rails of memory system | Physics | 2 | Active |
| US11424233B1 | Memory circuits and related methods | Electricity | 2 | Active |
| US11410740B2 | Multi-fuse memory cell circuit and method | Electricity | 2 | Active |
| US11810635B2 | Sense amplifier for coupling effect reduction | Electricity | 1 | Active |
| US11094701B2 | Layout structure of storage cell and method thereof | Electricity | 1 | Active |
| US11681468B2 | Memory device for scheduling maximum number of memory macros write operations at re-arranged time intervals | Emerging Cross-Sectional Technologies | 1 | Active |
| US12014768B2 | DRAM computation circuit and method | Electricity | 1 | Active |
| US11653492B2 | Memory devices and methods of manufacturing thereof | Performing Operations; Transporting | 1 | Active |
| US11605427B2 | Memory device with write pulse trimming | Physics | 1 | Active |
| US11682433B2 | Multiple stack high voltage circuit for memory | Physics | 1 | Active |
| US11749664B2 | Memory circuits | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.