Three-dimensional memory device containing through-memory-level contact via structures
US10971507B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Oct 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first alternating stack of first insulating layers and first sacrificial material layers with first stepped surfaces is formed over a substrate. A first retro-stepped dielectric material portion is formed on the first stepped surfaces. A second alternating stack of second insulating layers and second sacrificial material layers with second stepped surfaces is formed over the first alternating stack. A second retro-stepped dielectric material portion is formed on the second stepped surfaces. A first conductive via structure is formed through the second retro-stepped dielectric material portion, a bottommost insulating layer of the second alternating stack, and the first retro-stepped dielectric material portion. The sacrificial material layers are replaced with electrically conductive layers. The first conductive via structure is electrically connected to a first electrically conductive layer that replaces a first sacrificial material layer, and is electrically isolated from each second electrically conductive layer in the second alternating stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.