Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same
US10971514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Mar 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.