Chip ESD protection circuit
US10971929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2016 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Dec 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.