Multiplier-accumulator circuitry, and processing pipeline including same
US10972103B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 2020 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | May 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17724
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a plurality of multiply-accumulator circuitry, configurable in a concatenation architecture, to perform a plurality of multiply and accumulate operations, wherein the plurality of multiply-accumulator circuitry is organized into a plurality of groups, including a first group of multiply-accumulator circuitry and a second group of multiply-accumulator circuitry, wherein each group includes: a plurality of MAC circuits, each including a multiplier to multiply data by a multiplier weight data and generate a product data, and an accumulator to add input data and the product data to generate sum data, and wherein the plurality of MAC circuits of each group is organized in at least one row and connected in series to perform a plurality of concatenated multiply and accumulate operations. The integrated circuit also includes configurable interface circuitry to connect and/or disconnect the plurality of MAC circuits of the first and second groups of multiply-accumulator circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.