Phase and delay compensation circuit and method
US10972106B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2020 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Nov 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay balancing circuit includes a phase detection circuit, a controller, and a delay circuit. The phase detection circuit receives a reference clock signal having a first frequency, and a feedback clock signal derived from an output clock signal. Detection circuitry detects a phase relationship between the reference clock signal and the feedback clock signal. The phase detection circuit generates a detection signal based on the detected phase relationship. The controller operates to sample the detection signal and to generate and pass an update signal to a delay line to update a delay based on the sampled value. The delay circuit receives a third clock signal and applies a delay, based on the update signal, to the third clock signal to generate the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.