Integrated circuit including load standard cell and method of designing the same
US10977412B2 · kind B2 · utility
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9References
20Claims
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Key dates
| Filing date | Oct 18, 2018 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.