Memory cell, memory cell arrangement and methods thereof
US10978129B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 15, 2020 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Jul 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is provided that may include: a field-effect transistor structure including a channel and a gate structure disposed adjacent to the channel, the gate structure including: one or more remanent-polarizable layers, a gate electrode, wherein the one or more remanent-polarizable layers are disposed between the gate electrode and the channel, and one or more charge storage structures disposed between at least one of the one or more remanent-polarizable layers and the channel and/or the one or more remanent-polarizable layers and the gate electrode, the one or more charge storage structures are configured to stabilize a polarization state associated with the one or more remanent-polarizable layers by trapping charge in the one or more charge storage structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.