Dual-mode high-bandwidth SRAM with self-timed clock circuit
US10978139B2 · kind B2 · utility
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15References
11Claims
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Key dates
| Filing date | Jun 4, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Jun 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.