Keith Alan Bowman
41Patents
6h-index
57Co-inventors
68Inventor score
Filing activity: Jun 5, 2007 → Jul 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10009016B1 | Dynamically adaptive voltage-frequency guardband control circuit | Emerging Cross-Sectional Technologies | 18 | Active |
| US9413344B2 | Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems | Electricity | 17 | Active |
| US9628089B1 | Supply voltage tracking clock generator in adaptive clock distribution systems | Electricity | 14 | Active |
| US9251875B1 | Register file circuit and method for improving the minimum operating supply voltage | Physics | 12 | Active |
| US10587253B1 | Ring oscillator-based programmable delay line | Electricity | 11 | Active |
| US11249530B1 | Adaptive voltage controller | Physics | 8 | Active |
| US7653850B2 | Delay fault detection using latch with error sampling | Physics | 6 | Active |
| US9842634B2 | Wordline negative boost write-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) write port(s), and related systems and methods | Physics | 6 | Active |
| US9229054B2 | Self-contained, path-level aging monitor apparatus and method | Physics | 6 | Active |
| US11424736B1 | Adaptive clock duty-cycle controller | Electricity | 6 | Active |
| US8301970B2 | Sequential circuit with error detection | Electricity | 5 | Active |
| US9940992B2 | Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell | Physics | 4 | Active |
| US9625924B2 | Leakage current supply circuit for reducing low drop-out voltage regulator headroom | Electricity | 4 | Active |
| US9741452B2 | Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and related memory systems and methods | Electricity | 3 | Active |
| US11398812B1 | Adaptive clock duty-cycle controller | Electricity | 2 | Active |
| US10024916B2 | Sequential circuit with error detection | Physics | 2 | Active |
| US9984730B2 | Negative supply rail positive boost write-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) write port(s), and related systems and methods | Physics | 1 | Active |
| US10163490B2 | P-type field-effect transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells, and related memory systems and methods | Physics | 1 | Active |
| US9772903B2 | Resilient register file circuit for dynamic variation tolerance and method of operating the same | Physics | 1 | Active |
| US10026456B2 | Bitline positive boost write-assist circuits for memory bit cells employing a P-type Field-Effect transistor (PFET) write port(s), and related systems and methods | Physics | 1 | Active |
| US11264976B2 | Symmetrically-interconnected tunable time delay circuit | Electricity | 1 | Active |
| US9915968B2 | Systems and methods for adaptive clock design | Electricity | 1 | Active |
| US10622043B2 | Multi-pump memory system access circuits for sequentially executing parallel memory operations | Physics | 1 | Active |
| US9330785B1 | Read operation based aging sensor for static random access memory (SRAM) | Physics | 1 | Active |
| US11493980B1 | Power controller communication latency mitigation | Emerging Cross-Sectional Technologies | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.