Pre-cleaning a semiconductor structure
US10978291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2014 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Jan 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76814
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method of pre-cleaning a semiconductor structure and to associated modular semiconductor process tools. The method includes the steps of: (i) providing a semiconductor structure having an exposed dielectric layer of an organic dielectric material, wherein the dielectric layer has one or more features formed therein which expose one or more electrically conductive structures to be pre-cleaned, in which the electrically conductive structures each include a metal layer, optionally with a barrier layer formed thereon, and the surface area of the exposed dielectric layer is greater than the surface area of the electrically conductive structures exposed by the dielectric layer; and (ii) pre-cleaning the semiconductor structure by performing an Ar/H2 sputter etch to remove material from the exposed electrically conductive structures and to remove organic dielectric material from the exposed dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.