Method and system of manufacturing conductors and semiconductor device which includes conductors
US10978439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Aug 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of generating a layout diagram includes: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.