Patent · US Active

Method and apparatus for multi-voltage domain sequential elements

US10979034B1 · kind B1 · utility

2Cited by

4References

16Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Kumar Rahul · Andover, US
Santosh Yachareni · San Diego, US
Jitendra Kumar Yadav · Bengaluru, IN
Md Nadeem Iqbal · Supaul, IN
Teja Masina · Hyderabad, IN
Sourabh Swarnkar · Hyderabad, IN
Suresh Babu Kotha · Hyderabad, IN

Key dates

Filing date	Jun 19, 2018
Grant date	Apr 13, 2021
Priority date	—
Expiry date	Jun 19, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/018557
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.