Successive approximation register analog to digital converter based phase-locked loop with programmable range
US10979059B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2020 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Oct 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/189
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described herein are apparatus and methods for a successive approximation register (SAR) analog-to-digital (ADC) based phase-locked loop (PLL) with programmable range. A multi-bit digital phase locked loop includes a multi-bit phase frequency detector configured to output a multi-bit error signal based on a reference clock, a feedback clock sampled using the reference clock, and a threshold voltage, a multi-bit digital low pass filter configured to apply a variable gain to the multi-bit error signal, a current steered digital-to-analog converter configured to generate a control current based on a gain applied multi-bit error signal and multi-bit digital phase locked loop control parameters, a controlled oscillator configured to adjust a frequency of the controlled oscillator based on the control current to generate an output clock, the feedback clock being based on the output clock, and a programmable edge time controller configured to adjust a slope of an edge of the feedback clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.