Synchronization headers for serial data transmission with multi-level signaling
US10979210B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Jul 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3488
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Techniques for handling synchronization headers for serial data transmission with multi-level signaling are described. In an example, a transmitter includes a multiplexer circuit configured to serialize an input signal to generate an output bit sequence having a plurality of bits between pairs of synchronization header bits. The transmitter includes a re-ordering circuit, coupled to the multiplexer circuit to receive the output bit sequence, configured to re-order the output bit sequence by moving at least one of the plurality of bits between the synchronization header bits in each of the pairs of synchronization header bits. The transmitter includes an output driver circuit configured to drive the re-ordered output bit sequence onto a transmission medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.