Patent · US Active

RAM memory with pre-charging circuitry coupled to global bit-lines and method for reducing power consumption

US10984843B2 · kind B2 · utility

0Cited by

7References

9Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Martin Bernhard Schmidt · Stuttgart, DE
Harry Barowski · Balingen, DE
Simon Brandl · Stuttgart, DE
Wolfgang Penth · Holzgerlingen, DE

Key dates

Filing date	Mar 1, 2019
Grant date	Apr 20, 2021
Priority date	—
Expiry date	Mar 1, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/814
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory cell arrangement for Random Access Memory (RAM) including one or more RAM cell groups. The RAM cell groups having two or more local bit-lines sharing a Global Bit-Line (GBL), a pre-charging circuit connected to the GBL, a multiplexer connected to multiple GBLs and configured to shift an output of a first GBL from a first bit to a second bit at least in part according to a value of a fuse bit register associated with a second GBL, and at least one pre-charge enabling circuit controlled by a combination of a pre-charge input value applied to all GBLs of the memory cell arrangement and a pre-charge enable signal for the GBL.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.