Patent · US Active

Error detection and correction circuitry

US10984863B2 · kind B2 · utility

1Cited by

32References

19Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Mohammed Saif Kunjatur Sheikh · Bengaluru, IN
Vikash · Bengaluru, IN
Andy Wangkun Chen · Austin, US

Key dates

Filing date	Apr 20, 2018
Grant date	Apr 20, 2021
Priority date	—
Expiry date	Feb 1, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/0411
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having an array of bitcells. The integrated circuit may include latch circuitry having a latch for each row of bitcells that latches valid match data into the latch for each row of bitcells. The integrated circuit may include priority encoding circuitry that receives the valid match data from the latch for each row of bitcells. The integrated circuit may include first logic circuitry coupled between the array of bitcells and the priority encoding circuitry to assist with providing the valid match data to the latch circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.